Error (10500): VHDL syntax error at cj200.vhd(17) near text ":="; expecting "(", or "'", or "."LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY cj200 IS PORT (CLK :IN STD_LOGIC; DB:INOUT STD_LOGIC_VECTOR(

Error (10500): VHDL syntax error at cj200.vhd(17) near text ":="; expecting "(", or "'", or "."LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY cj200 IS PORT (CLK :IN STD_LOGIC; DB:INOUT STD_LOGIC_VECTOR(
Error (10500): VHDL syntax error at cj200.vhd(17) near text ":="; expecting "(", or "'", or "."
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY cj200 IS
PORT (CLK :IN STD_LOGIC;
DB:INOUT STD_LOGIC_VECTOR(7 DOWNTO 0);
AB:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
CS:OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
RD:OUT STD_LOGIC;
WR:OUT STD_LOGIC);
END cj200;

ARCHITECTURE TESTDA OF cj200 IS
VARIABLE ys : INTEGER;
VARIABLE x : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
x := "00000000";
LOL:LOOP
ys:=0;
DB

Error (10500): VHDL syntax error at cj200.vhd(17) near text ":="; expecting "(", or "'", or "."LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY cj200 IS PORT (CLK :IN STD_LOGIC; DB:INOUT STD_LOGIC_VECTOR(
初步看了一下,process不可以放在loop循环里面,还有变量VARIABLE只能在process里面用